Test structures for characterization of through silicon vias

Abstract

As silicon technology reaches extreme sub-um dimensions, the industry has reached for “more than Moore” solutions to enable advancements in integration, lower system cost, and improve packaging footprints. Probably the best known of the more-than-Moore solutions is 3D chip stacking using through silicon vias (TSVs). This technology requires accurate characterization of the TSV, the thinned silicon, and the stacked die. Our paper deals with TSV characterization by means of specially designed test structures.