Prediction of Test Pattern Count and Test Data Volume for Scan Architectures under Different Input Channel Configurations

Abstract

As the complexity of industrial integrated circuits continue to increase rapidly, test data compression has now become a de facto technology for large designs to reduce the overall test cost. During the design for test (DFT) planning, it is critical to understand the impact of using different numbers of input/output test channels on test coverage, test cycles, and test data volume. In this paper, two approaches to predict the test pattern counts and test data volumes with different input channel counts are presented, one with the compression tool able to generate channel-scaling patterns and the other without this capability. The results can be used to determine the scan test configuration that results in the smallest or near smallest test data volume. Experiments on industrial circuits show that the average error rates of pattern count prediction for most circuits are less than 10% for both approaches. The error rates of the predicted smallest data volumes are all less than 3.5%. The total ATPG run time can be reduced by a factor of more than 10X compared to the currently used trial-and-error approach.