Method of Determining Reliability Screens for Time Dependent Dielectric Breakdown

Abstract

Time dependent dielectric breakdown on MOS LSI circuits is a function of stress voltage, temperature, device area and latent defect density. A model for time dependent dielectric breakdown as a function of these parameters has been developed. This model has been empirically verified on test structures, as well as actual memory devices. A discussion of how this model is used to determine reliability screens for time dependent dielectric breakdown is presented.