Automated antenna detection and correction methodology in VLSI designs

Abstract

As more and more devices are packed on a single chip and as the complexities of VLSI designs are increasing, antenna detection and correction is becoming an increasingly challenging task. The paper presents a methodology, which employs a combination of prevention and correction of antennae at various stages of ASIC (Application specific Integrated Circuits) design flow such as cell library development, block design flow and chip design flow. The methodology advocates adding protection diodes only in a certain number of cells in the library. We have implemented this methodology in our ASIC design flow and are able to solve antenna issues in designs with negligible impact on die size (24% increase in die-size in less than 5% of the designs) and performance (0.3%-0.6% worst case impact to delay). By employing this methodology, we found that the number of antennae in the final layout reduced to very small number and even to zero in some cases, and we were able to save the time involved in correcting antennae.