Block-Based Finite Element Modeling, Simulation, and Optimization of the Warpage of Embedded Trace Substrate

Chien-Yu Lien, Yao-Chen Chuang, Yuan Yao, Edward Charn, Eric Chen
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引用次数: 3

Abstract

As the electronic devices getting lighter and smaller, a coreless substrate technology, called Embedded Trace Substrate (ETS) is developed to meet the market requirement. However, this design causes severe warpage due to the large difference in CTE (coefficient of thermal expansion) of buildup material and Cu plate. Recently, finite element analysis (FEA) is a popular and effective method used for substrate warpage prediction and mechanical studies. Manufacturers apply FEA simulation for substrate design improvements and provide substrate warpage that satisfying the customer’s specification. Nevertheless, the computational resources needed for high-fidelity simulation are extremely expensive and time-consuming. Hence the simulation study becomes a long and arduous task if it has to be performed many times, e.g., sensitivity analysis and warpage optimization.In this paper, we propose a new method for FEA modeling of mechanical behaviors of the substrate and present an optimization strategy for substrate warpage control. In the first step, the Gerber files of each layer of the substrate are converted into high-resolution bitmap images, and the copper area of each image is divided and scanned by a pre-sized block window. After that, the effective material properties for each block are calculated with a volume average micromechanics approach, and then all blocks are stacked-up to build a block-based analysis model for FEA simulation. As compared with conventional trace mapping simulation, the proposed method significantly decreases the demands of the computing resource. Besides, we gained accurate warpage prediction results as validated by a real substrate experiment. Finally, we presented an optimization strategy that manipulates the thickness of each layer for substrate warpage optimization in pre-processing steps of packaging. In conclusion, the results show that the methodology for substrate simulation in this paper is practical, effective, and costless.
嵌入式轨迹基板翘曲的基于块的有限元建模、仿真和优化
随着电子器件的轻量化和小型化,一种无芯基板技术应运而生,称为嵌入式走线基板(ETS)。然而,这种设计导致严重的翘曲,由于CTE(热膨胀系数)的累积材料和铜板的差异很大。近年来,有限元分析(FEA)是一种广泛而有效的用于基材翘曲预测和力学研究的方法。制造商应用有限元模拟来改进基板设计,并提供满足客户规格的基板翘曲。然而,高保真仿真所需的计算资源非常昂贵且耗时。因此,如果需要多次进行模拟研究,例如灵敏度分析和翘曲优化,则模拟研究将成为一项漫长而艰巨的任务。本文提出了一种新的基板力学行为有限元建模方法,并提出了基板翘曲控制的优化策略。第一步,将基材每层的Gerber文件转换成高分辨率的位图图像,并通过预大小的块窗对每张图像的铜区域进行分割和扫描。然后,采用体积平均细观力学方法计算各块体的有效材料性能,然后将各块体进行叠加,建立基于块体的分析模型进行有限元仿真。与传统的轨迹映射仿真相比,该方法显著降低了对计算资源的需求。此外,我们还得到了准确的翘曲预测结果,并通过实际的衬底实验进行了验证。最后,我们提出了一种优化策略,可以在封装的预处理步骤中操纵每层的厚度来优化基板翘曲。综上所述,本文所提出的基板模拟方法是实用、有效且无成本的。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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