A 12 bit 1.6 GS/s BiCMOS 2×2 hierarchical time-interleaved pipeline ADC

Abstract

A 12 bit 1.6 GS/s pipeline ADC realized in a 0.18 μm complementary BiCMOS SiGe process is presented. The ADC consists of a four-way time-interleaved hierarchical structure and a master-slave T/H to improve the dynamic performance of the individual sub-ADCs and to reduce both the complexity of the required interleaving background calibration algorithms and the error rate. It achieves an SFDR of 79 dBc at low frequency inputs and 66 dBc at Nyquist, and has an error rate of less than 10-9.