Heuristic Approach for Identification of Random TSV Defects in 3D IC During Pre-bond Testing

Abstract

The possibility of 3D integrated circuit (3D IC) has been considered as a choice to overcome the difficulties faced by two-dimensional integrated circuits (2D IC). Several technologies exist to connect the layers in 3D IC. Among these technologies through-silicon vias (TSVs) is the promising one since it helps to reduce interconnect length, delays and power consumption. In spite of the advantages it introduces different types of defects which ultimately make an entire IC faulty. Thus, testing of TSVs is an important necessity. Depending on the timing, the testing may be of two types -pre-bond and post-bond. In pre-bond TSV testing TSVs are tested in sessions. In this paper our objective is to reduce the pre-bond TSV test sessions as much as possible, so that overall testing time decreases. To reduce test sessions we need to reduce the individual TSV testing and increase group wise TSV testing.