Reverse Elevated Source/Drain (RESD) MOSFET for deep submicron CMOS

Abstract

A new Reverse Elevated Source/Drain (RESD) CMOS process has been developed as part of a deep submicron CMOS technology featuring ultra-shallow source/drain junctions with reversed (with respect to epi formation) phosphorus LDD implantation. This new structure utilizes disposable nitride spacers to define the selective silicon offset from the gate edge prior to LDD implantation. Since the LDD junctions are not exposed to the high temperature prebake and deposition conditions, shallow phosphorus junctions provide improved short-channel behavior while maintaining good hot-carrier protection.<>