iProbe-d: a hot-carrier and oxide reliability simulator

Abstract

In this paper we describe a hot-carrier and oxide reliability simulator, iProbe-d. In this program, a probabilistic timing approach is employed to find the most susceptible devices to hot-carrier degradation and/or oxide breakdown in a CMOS VLSI digital circuit design under expected operating conditions. After the damage in each device is determined, a combination of damaged-transistor model, RC delay and critical path analysis is used to estimate the impact of hot-carrier effects (HCE) on circuit performance; namely, the increase of circuit delay. The results can then be used to improve the reliability of the circuit prior to fabrication.<>