Reducing the susceptibility of design-for-delay-testability structures to process- and application-induced variations

Abstract

Recently, a new type of Design-for-Delay-Testability structure and associated Built-In Self-Test architecture for detecting delay faults in digital high-performance circuits has been proposed. It circumvents the requirement of an expensive high-speed tester. In this paper, the susceptibility of the proposed structure to process- and application-induced variations has been investigated. Due to the critical timing necessary when detecting small delay faults it is crucial to know what to expect from these variations and subsequently reduce their influence.