Design of Special Chips for Relay Protection Based on Dual High-Performance SoC

Abstract

From the perspective of improving the speed and reliability of power system relay protection, this paper proposes a relay protection hardware design based on dual high-performance SoC. In the design, the parallel redundant software and hardware system architecture is used to realize separate and independent operations of protection function and startup function, with heterogeneous asymmetric multiprocessing mode and off-chip DDR controller that supports ECC error correction adopted to ensure the strict real-time performance and data reliability of protection sampling and calculation functions. Furthermore, by the method of integrating AD sampling preprocessing module and FFT acceleration processor in the on-chip high-performance FPGA, the speed of relay protection data processing and actions are improved.