Y. Ohji, Y. Matsui, T. Itoga, M. Hirayama, Y. Sugawara, K. Torii, H. Miki, M. Nakata, I. Asano, S. Iijima, Y. Kawamoto
{"title":"Ta/sub 2/O/sub 5/ capacitors' dielectric material for giga-bit DRAMs","authors":"Y. Ohji, Y. Matsui, T. Itoga, M. Hirayama, Y. Sugawara, K. Torii, H. Miki, M. Nakata, I. Asano, S. Iijima, Y. Kawamoto","doi":"10.1109/IEDM.1995.497194","DOIUrl":null,"url":null,"abstract":"We fabricated 256-Mbit DRAM cells using a 0.5 /spl mu/m high CROWN capacitor with crystallized Ta/sub 2/O/sub 5/ dielectric film. We confirmed that the crystallized Ta/sub 2/O/sub 5/ (3.3 nm of SiO/sub 2/-equivalent thickness) was very stable in the conventional metallization process. The key issues for manufacturing were to eliminate the hydrocarbon contaminants during high temperature O/sub 2/ annealing. Our preliminary investigation of Ta/sub 2/O/sub 5/ metal-insulator-metal (MIM) capacitors suggested that it is possible to fabricate 1-Gbit DRAM cells using the amorphous Ta/sub 2/O/sub 5/ MIM capacitor with a CROWN structure.","PeriodicalId":137564,"journal":{"name":"Proceedings of International Electron Devices Meeting","volume":"27 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of International Electron Devices Meeting","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.1995.497194","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 7
Abstract
We fabricated 256-Mbit DRAM cells using a 0.5 /spl mu/m high CROWN capacitor with crystallized Ta/sub 2/O/sub 5/ dielectric film. We confirmed that the crystallized Ta/sub 2/O/sub 5/ (3.3 nm of SiO/sub 2/-equivalent thickness) was very stable in the conventional metallization process. The key issues for manufacturing were to eliminate the hydrocarbon contaminants during high temperature O/sub 2/ annealing. Our preliminary investigation of Ta/sub 2/O/sub 5/ metal-insulator-metal (MIM) capacitors suggested that it is possible to fabricate 1-Gbit DRAM cells using the amorphous Ta/sub 2/O/sub 5/ MIM capacitor with a CROWN structure.