Printability study of EUV double patterning for CMOS metal layers

Abstract

The impending introduction of EUV lithography into high volume manufacturing at the 7 nm CMOS technology node promises the fulfilment of more than three decades of research and development. However, printing defect-free photoresist features with k1 < 0.4 or line-space pitch < 34 nm using 0.33 NA exposure tools is proving more challenging than originally anticipated. With the introduction timeline of 0.55 NA exposure tools currently unclear, it is necessary to develop EUV multiple patterning strategies for < 34 nm pitch metal layers which are needed to continue area scaling in future 5 nm and/or 3 nm technology nodes. Pursuing EUV-SADP strategies necessitates electrically undesirable dummification of metal wires and the employment of 2 additional masks for self-aligned cutting/blocking of wiring features which may prove cost prohibitive. Therefore, in this study we explore the printability in photoresist of two color EUV LELE or (litho-etch)2 patterns which may be further developed into self-aligned LELE patterning methods. We experimentally examine the impact of image and resist tonality on the printability of minimum line and space for metal wire features. We evaluate the printability of these features based on LCDU, LER, LWR and stochastics defects. Additionally, as EUV exposure time per mask is expected to be a major cost contributor, we quantitatively determine the impact of resist photo-speed on the printability of these two color LELE features.