Extreamly Advanced Cu Interconnect with Selective ALD Barrier for High Performance Logic Device

Abstract

In this paper, selective atomic layer deposition (ALD) TaN barrier process was described for advanced high performance logic device. Compared to conventional ALD deposited barrier, selective barrier adopted process showed 40% lower via resistance and comparable electrical healthiness at various via test structures. By applying this process, we achieved better chip performance and comparable chip yield using internal foundry product. This result demonstrates manufacturability of a selective barrier for advanced high performance logic device. Keywords—Cu; Barrierless, ALD TaN;