A self-aligned split-gate flash EEPROM cell with 3-D pillar structure

1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325) Pub Date : 1999-06-14 DOI:10.1109/VLSIT.1999.799353

F. Hayashi, J. Plummer

引用次数: 1

Abstract

A novel 3D memory cell has been proposed for high density future generation flash EEPROMs. A self-aligned split-gate (SASG) structure, minimizing the split-gate length, has been implemented in a pillar-shape cell with high scalability over the tunnel oxide scaling limitation. This cell technology allows an ideal split-gate cell size of 6F/sup 2/. Good programming and erase characteristics have been obtained and over-erasing has been suppressed down to a 0.1 /spl mu/m split-gate length in experimental devices.

查看原文本刊更多论文

一种具有三维柱状结构的自对准分栅闪存EEPROM单元

提出了一种用于高密度下一代闪存eeprom的新型三维存储单元。在柱状电池中实现了一种自对准分栅(SASG)结构，最大限度地减少了分栅长度，具有高可扩展性，超过了隧道氧化物的结皮限制。这种电池技术允许理想的分栅电池尺寸为6F/sup /。在实验装置中获得了良好的编程和擦除特性，并将过擦除抑制到0.1 /spl mu/m的分栅长度。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

求助全文

约1分钟内获得全文求助全文

来源期刊

1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325)

自引率

0.00%

发文量