Bus Snubber Optimization for Multi-Chip Power Modules using SPICE Simulations

Abstract

Bus snubbers are a commonly used mechanism for improving the switching performance of circuits using wide bandgap devices. Particularly, their influence on switching losses and transient overshoot is of interest. However, bus snubbers can have multiple effects on these behaviors, resulting in a series of tradeoffs. Understanding the tradeoffs associated with bus snubber design can assist in selecting an optimal value for a given system, but determining this optimal value empirically is challenging and time consuming. As such, this paper leverages a SPICE simulation model of a multi-chip power module and accompanying application circuit to analyze these trends. This simulation model is empirically validated with a set of experiments performed on a double pulse test stand. The resulting analysis demonstrates that the presented SPICE model can facilitate the selection of an optimal bus capacitor, thereby reducing the need for empirical analysis. The effect of additional resistance in the snubber circuit is also analyzed empirically, revealing further tradeoffs to be considered for snubber design.