Hot-electron-induced input offset voltage degradation in CMOS differential amplifiers

Abstract

A key figure of merit for high-precision/performance circuit applications is the input offset voltage, which is defined as the differential input voltage necessary to produce a zero differential output voltage. The impact of hot-electron degradation on the input offset voltage of a CMOS differential amplifier is characterized. The NMOS and PMOS transistors examined were fabricated using a 1.5- mu m LOCOS-isolated, double-metal, BiCMOS process for mixed signal applications. Using the concept of a virtual source-coupled pair, may aspects of V/sub Offset/ degradation are determined directly from individual device measurements. Techniques are developed for estimating V/sub Offset/ device lifetime under operational conditions from accelerated stress measurements. Analytical models for V/sub Offset/ degradation are also developed. Performance and reliability tradeoffs for different CMOS differential amplifier designs are analyzed.<>