Reduction of overhead in adaptive body bias technology due to triple-well structure based on measurement and simulation

Y. Ogasahara, T. Sekigawa, M. Hioki, T. Nakagawa, T. Tsutsumi, H. Koike
{"title":"Reduction of overhead in adaptive body bias technology due to triple-well structure based on measurement and simulation","authors":"Y. Ogasahara, T. Sekigawa, M. Hioki, T. Nakagawa, T. Tsutsumi, H. Koike","doi":"10.1109/ICMTS.2015.7106154","DOIUrl":null,"url":null,"abstract":"This paper presents the significant reduction of the area overhead due to triple-well structure for adaptive body bias methods. Triple-well TEGs which include violation of design rules originating from voltage tolerance were implemented on a 65nm process. Reexamining voltage tolerance based on measurement results reduced deep n-wells spacing by 60% on the 65nm process. A new method for further overhead reduction is proposed based on a device simulation which is validated with measurement results.","PeriodicalId":177627,"journal":{"name":"Proceedings of the 2015 International Conference on Microelectronic Test Structures","volume":"45 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 2015 International Conference on Microelectronic Test Structures","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICMTS.2015.7106154","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2

Abstract

This paper presents the significant reduction of the area overhead due to triple-well structure for adaptive body bias methods. Triple-well TEGs which include violation of design rules originating from voltage tolerance were implemented on a 65nm process. Reexamining voltage tolerance based on measurement results reduced deep n-wells spacing by 60% on the 65nm process. A new method for further overhead reduction is proposed based on a device simulation which is validated with measurement results.
基于测量和仿真的三井结构自适应体偏技术降低开销
本文介绍了自适应体偏法中由于三井结构而显著减少的面积开销。在65nm工艺上实施的三井teg违反了电压容限的设计规则。根据测量结果重新检查电压容差,在65nm工艺中,深n井间距减少了60%。在器件仿真的基础上,提出了一种进一步降低开销的新方法,并与实测结果进行了验证。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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