S. Wright, P. Andry, E. Sprogis, B. Dang, R. Polastre
{"title":"Reliability testing of through-silicon vias for high-current 3D applications","authors":"S. Wright, P. Andry, E. Sprogis, B. Dang, R. Polastre","doi":"10.1109/ECTC.2008.4550080","DOIUrl":null,"url":null,"abstract":"A robust through-silicon via technology is necessary for high-power, high-performance 3D-silicon applications. To study through-via interconnection reliability, modules consisting of a test chip, silicon carrier interposer with through-vias, and ceramic substrate were constructed. A socket assembly containing a microchannel water cooler was also constructed to apply pulsed power to via daisy chain test sites. Test results to date indicate that the interconnection reliability is limited by the solder bump portions of the interconnection, not the through-silicon via itself.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"13","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 58th Electronic Components and Technology Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ECTC.2008.4550080","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 13
Abstract
A robust through-silicon via technology is necessary for high-power, high-performance 3D-silicon applications. To study through-via interconnection reliability, modules consisting of a test chip, silicon carrier interposer with through-vias, and ceramic substrate were constructed. A socket assembly containing a microchannel water cooler was also constructed to apply pulsed power to via daisy chain test sites. Test results to date indicate that the interconnection reliability is limited by the solder bump portions of the interconnection, not the through-silicon via itself.