Comparison of Level Shifter Architectures: Application to I/O Cell

Abstract

Novel low-voltage and high-speed level shifter topologies will be presented. The level shifters circuits were designed in 40 nm technology using 1.2V devices and zero-VT transistors. These techniques will provide functionality near the threshold region. The simulated results were compared with a reference architecture. The resulted level shifters will be integrated in an already tested I/O structure. The results were analyzed in terms of electrical performance and silicon area.