Experiences In Deep Sub-Micron Scan-Based At-Speed Delay Testing

Abstract

As semiconductor process technologies keep improving, more and more high frequency chips will be designed and manufactured. Testing of timing-related defects thus is becoming essential to guarantee high quality deep sub-micron products. In this paper, we presented our experiences in scan-based at-speed delay testing. Based on transition delay and path delay fault model, we enhance the traditional production test flow with scan-based at-speed delay tests. To test chips at operational speed, we designed an on-chip test clock generator to generate at-speed launch-capture clock pulses. Therefore, high-speed testers will not be required. Commercial EDA tools are used for test pattern generation and timing analysis. In addition, stress test flow is proposed to enhance the test quality. Experimental results show that our approach can detect delay defects, which can be correlated with results of at-speed functional tests