Drain bias stress-induced degradation in amorphous silicon thin film transistors with negative gate bias

Abstract

In this study, degradation of amorphous silicon thin film transistors (a-Si TFTs) under drain bias (Vd) stresses with fixed negative gate bias (Vg) has been investigated. For DC Vd stress, state creation mechanism dominates the threshold voltage (Vth) degradation for relative large negative Vgd (Vg−Vd) while state creation and/or electron trapping dominates for positive Vgd. For AC Vd stress, state creation, electron trapping and hole trapping contribute to the degradation. Dominant mechanism depends on stress time, frequency and the polarity of Vgd. Decreasing stress voltage suppresses state creation and/or hole trapping for −Vgd condition, but enhances state creation and/or electron trapping for +Vgd condition.