Bond Pad Optimization for CMOS Imager with Chip Scale Package

Abstract

Three novel CSP pad designs in a 0.18mum CMOS image sensor Cu interconnect technology were analyzed for use with a wafer level CSP (WLCSP) package. The CSP pad designs used various combinations of available aluminum and tungsten interconnect levels in order to improve the cross-sectional area without increasing the total stack height of the Cu interconnect technology. It was found that by increasing the cross-sectional area of the CSP pads the T-connections formed in the CSP process had improved (tighter) resistance distributions