Study of a 3D phenomenon during ESD stresses in deep submicron CMOS technologies using photon emission tool

Abstract

The purpose of this work is to present a new phenomenon in the ElectroStatic Discharge (ESD) failure threshold of deep submicron CMOS technologies. Although the bipolar conduction mode (or snapback) used for the protection was considered as uniform, we present dynamic EMission MIcroscopy (EMMI) studies showing for the first time that the current does not instantly spread out over the complete width of the transistor. Furthermore, this phenomenon leads to a saturation of failure threshold for the widest transistors and plays a major part in the failure threshold of devices. Different parameters having an influence on the spreading of the current are analyzed and interesting conclusions for the design of ESD hard NMOS devices are drawn.