Metal inserted poly-Si with high temperature annealing for achieving EOT of 0.62nm in La-silicate MOSFET

Abstract

This paper reports device process approach for further EOT scaling with small interface state density based on controlling La-silicate/Si interface. The interface state density of 1.6 × 1011 cm−2 eV−1 can be achieved by annealing at 800 °C for 30min in forming gas while significant increase in EOT has been also observed. EOT increase caused by high temperature annealing has been drastically inhibited with MIPS stacks accompanied by high quality interface. The effective electron mobility of 155 cm2/Vsec at 1MV/cm with an EOT of 0.62 nm has been obtained in direct contact La-silicate/Si structure by combination of MIPS stacks with high temperature annealing.