A method for modeling the manufacturability of IC designs

Abstract

A methodology for modeling the manufacturability of MOS transistors and circuits is developed. The models are based on a small set of measurable process characterization parameters, whose variation explains the range of performance seen during production. A statistical MOSFET model, based on these measurable process parameters, is developed using global optimization and regression modeling of key fitting parameters in order to accurately predict transistor characteristics over a wide range of process variation. These same process parameters can be measured on the manufacturing floor, both in-line and at electrical test, and can be used to predict the performance of the fabricated integrated circuit before packaging and final test. The models for use in manufacturing and design are integrated. Data taken from the manufacturing line can be used to identify process shifts, as well as to suggest design improvements for manufacturability enhancement.<>