Communication graph and timing configuration for virtual components

Abstract

SOC design requires connecting and integrating intellectual property (IP) and virtual components (VC) from various sources. Among factors limiting IP reuse is their communications and interface incompatibility. IP integrators do not need to know and to understand how an IP is implemented, but they need a simple model describing its communication behavior, in addition to physical interface spec and timing diagrams. In the first part of this paper, we present a graph model to describe the communication behavior of a component including its timing constraints and flexibility. This model abstracts the functionality of the component and its implementation. In the second part, we present a method for timing analysis and configuration based on the communication behavior graph.