Studying Asymmetric Warpage Behavior of Panel-Level Packages Using Process Modeling Techniques and Viscoelasticity Theory

Abstract

Panel Level Packaging (PLP) is an integrated circuit (IC) packaging technology that is mainly used in fields such as mobile communications, consumer electronics, and industrial automation. Compared to wafer-level packaging, the advantages of panel-level packaging include improving manufacturing efficiency, reducing costs, and improving product quality. However, because the overall area of panel-level packaging is larger, there may be some problems in the manufacturing process, such as insufficient flatness of the substrate surface, poor adhesion between the substrate and the components, and incorrect component positioning. These problems may lead to poor product quality, asymmetric warpage, and even packaging failure.This paper aims to discuss the factors that may cause warpage in the panel-level packaging (PLP) process, including material non-uniformity, thermal stress, and mechanical stress. To address these issues, design and optimization of the packaging, selection of appropriate materials and process parameters, and stress analysis and simulation of the packaging are required. Through simulation, the warpage variation and stress distribution during the manufacturing process can be analyzed more efficiently. Our research will investigate the effects of different process parameters, such as the temperature of the molding process and the heating/cooling rate, as well as the thickness, size, and distribution of the encapsulant chips and other layers on warpage.