SIPI Co-Sim: Signal Performance of Super Speed Differential I/O with Power Referencing Design

Abstract

Printed circuit board (PCB) design with full ground referencing for high speed signaling is generally preferred for better or cleaner signal return path. However, this has become very challenging when platform design is trending toward a smaller and thinner form factor where having full ground layers in between PCB stack-up is no longer feasible for practical hardware implementation. With the increase in popularity to have signal-to-power referencing in PCB design, signal-integrity (SI) and power-integrity (PI) co-simulation is however not that straight forward and often comes with sophisticated co-sim’s assumptions. This is because signaling quality is impacted by noise coupling suffered by the signal which has high dependency on the power plane sizes and shapes, area of power referenced, as well as how well the power delivery network (PDN) design is. In this paper, we evaluate the SI performance of a super speed input/output (I/O) buffer with full ground plane or partial power plane as its return path. Three controlled electrical parameters - voltage threshold, peak-to-peak noise and frequency are varied in our studies to investigate the impact of power referencing to signal eye margin. From the study, it is shown that power referencing is doable for high-speed I/O on the conditions that the power referenced voltage rail is a low frequency rails that has dominant frequency contents in the range of less than 5% of the targeted signal operating frequency and the total peak-to-peak noise is below 330mVpp. With these findings, platform routing guidelines for I/O design could be more relaxed and flexible, by allowing partial power referencing to the high speed signal traces.