Analysis of HBM and MM ESD failures in nMOS devices

Abstract

The response and failure mechanisms of typical protection networks used in nMOS technology under simulated HBM and MM ESD stressing conditions are presented in this paper. The HBM stressing resulted in failures which are predominantly cumulative in nature, whereas MM stress caused abrupt and catastrophic failures. Under HBM stressing the failure modes are found to be increase in leakage current, resistive short and open circuit. The failures induced by MM stressing are mostly resistive short or open circuit. The failure analysis revealed the failure mechanisms to be contact spiking and electrothermomigration for those devices which do not have polysilicon strap in the protection circuit. Isolation oxide degradation and junction burn out following parasitic transistor turn-on are the failure mechanisms observed in those devices with the poly strap.