Influence of parasitic capacitances on switching characteristics of SOI-LDMOSs

Abstract

This paper describes the influence of parasitic capacitances on the switching characteristics of lateral DMOSFETs fabricated in Silicon on Insulator (SOI) substrates with silicon thicknesses from 1 to 20 /spl mu/m. The dependences of the parasitic capacitances, especially an additional drain-substrate capacitance attributed to the use of an SOI substrate, on the drift region length, silicon layer thickness and buried oxide thickness are confirmed experimentally. It is shown that optimization of these parameters is critical for high speed switching applications.