Impact of lithography variations on advanced CMOS devices

2009 International Symposium on VLSI Technology, Systems, and Applications Pub Date : 2009-04-27 DOI:10.1109/VTSA.2009.5159272

J. Lorenz, C. Kampen, A. Burenkov, T. Fuhner

引用次数: 3

Abstract

Source and relevance of process variations are briefly discussed. A combination of own lithography and commercial TCAD simulation software is applied to assess the impact of some of the most relevant variations occurring in lithography on the electrical properties of three kinds of CMOS devices with 32 nm physical gate length.

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光刻技术变化对先进CMOS器件的影响

简要讨论了过程变化的来源和相关性。结合自己的光刻工艺和商用TCAD仿真软件，评估了光刻工艺中一些最相关的变化对三种物理栅长为32 nm的CMOS器件电学性能的影响。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

2009 International Symposium on VLSI Technology, Systems, and Applications

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