Process variability considerations in the design of an eSRAM

Abstract

Process variation constitutes a serious hindrance to the performance of SRAMs, since memories require bigger design margins for their proper operations. In this paper, we propose a new dummy bit line driver structure and its statistical sizing method to reduce the sensitivity of the memory with respect to process variations, while improving the read timing margin. The dummy bit line driver is an essential component in a self-timed memory during a read operation. It triggers the sense amplifier at the appropriate time when bit line is discharged. We considered a 256 kb SRAM in a 90 nm technology node.