Multi-Level Air Gap Integration for 32/22nm nodes using a Spin-on Thermal Degradable Polymer and a SiOC CVD Hard Mask

R. Daamen, P. Bancken, D. Emur Badaroglu, J. Michelon, V. Nguyen, G. Verheijden, A. Humbert, J. Waeterloos, A. Yang, J. K. Cheng, L. Chen, T. Martens, R. Hoofman
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引用次数: 13

Abstract

In this work, we propose and verify a robust dual damascene air gap architecture, which avoids the increasing complexity and cost normally associated with current multilevel air gap integration. Air gap packaging reliability was also addressed showing promising stud bonding and wire pull test results. Furthermore two solutions are proposed to solve any possible un-landed via issues, including simultaneous air gap formation at multiple metal levels, which could even be used to reduce the thermal budget for the 32/22 nm nodes.
采用自旋热降解聚合物和SiOC CVD硬掩膜的32/22nm节点多级气隙集成
在这项工作中,我们提出并验证了一个强大的双大马士革气隙架构,它避免了当前多级气隙集成通常带来的复杂性和成本的增加。气隙封装的可靠性也得到了解决,显示出有希望的螺柱粘合和拉线测试结果。此外,提出了两种解决方案来解决任何可能的未着陆点问题,包括在多个金属层同时形成气隙,这甚至可以用来减少32/22 nm节点的热预算。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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