Design of Verification Platform for CAN-FD IP Customized SRAM Controller Based on UVM

Abstract

This article focuses on the design of a system-level verification platform for a static random-access memory (SRAM) module. The SRAM module is in a CAN-FD SOC chip. The SRAM memory controller verified by the verification platform in this paper is an important module integrated on the APB SOC chip bus for basic communication with CAN-FD IP. By adopting UVM universal verification methodology, a complete verification platform and verification environment suitable for the module are designed and built; by generating constrained random test excitation signals, the function of the controller is fully verified, and the results can be automatically compared with the data. The results show that the verification platform can greatly reduce the development time of verification incentives, simplify the verification process, shorten the verification cycle and have good reusability.