{"title":"Failure Analysis Techniques and Failure Mechanisms Utilizing a Plasma Etcher","authors":"J. Gajda, D. DeLorenzo, J. A. Wade","doi":"10.1109/IRPS.1979.362889","DOIUrl":null,"url":null,"abstract":"The utilization of plasma etching for selective layer removal of semiconductor device passivation films, polysilicon or substrate silicon, is playing a more and more significant role in delineation of specific failure mechanisms or process introduced anomalies. The advantages of selective removal of materials without destroying the failure site or its morphology are discussed, as well as complementary techniques used in performance of the various analyses. Analysis results are given involving bipolar and FET structures that identify 1. Sites of metal alloy penetration causing excessive leakage currents in bipolar logic circuitry. 2. Opens in test site double level metal interconnection vias due to current stress. 3. Corrosion sites on interconnection metallurgy. 4. FET gate oxide quality after polysilicon gate electrode removal. 5 Test site C-4 terminal interconnection via opens.","PeriodicalId":161068,"journal":{"name":"17th International Reliability Physics Symposium","volume":"136 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1979-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"17th International Reliability Physics Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IRPS.1979.362889","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
The utilization of plasma etching for selective layer removal of semiconductor device passivation films, polysilicon or substrate silicon, is playing a more and more significant role in delineation of specific failure mechanisms or process introduced anomalies. The advantages of selective removal of materials without destroying the failure site or its morphology are discussed, as well as complementary techniques used in performance of the various analyses. Analysis results are given involving bipolar and FET structures that identify 1. Sites of metal alloy penetration causing excessive leakage currents in bipolar logic circuitry. 2. Opens in test site double level metal interconnection vias due to current stress. 3. Corrosion sites on interconnection metallurgy. 4. FET gate oxide quality after polysilicon gate electrode removal. 5 Test site C-4 terminal interconnection via opens.