Failure Analysis Techniques and Failure Mechanisms Utilizing a Plasma Etcher

J. Gajda, D. DeLorenzo, J. A. Wade
{"title":"Failure Analysis Techniques and Failure Mechanisms Utilizing a Plasma Etcher","authors":"J. Gajda, D. DeLorenzo, J. A. Wade","doi":"10.1109/IRPS.1979.362889","DOIUrl":null,"url":null,"abstract":"The utilization of plasma etching for selective layer removal of semiconductor device passivation films, polysilicon or substrate silicon, is playing a more and more significant role in delineation of specific failure mechanisms or process introduced anomalies. The advantages of selective removal of materials without destroying the failure site or its morphology are discussed, as well as complementary techniques used in performance of the various analyses. Analysis results are given involving bipolar and FET structures that identify 1. Sites of metal alloy penetration causing excessive leakage currents in bipolar logic circuitry. 2. Opens in test site double level metal interconnection vias due to current stress. 3. Corrosion sites on interconnection metallurgy. 4. FET gate oxide quality after polysilicon gate electrode removal. 5 Test site C-4 terminal interconnection via opens.","PeriodicalId":161068,"journal":{"name":"17th International Reliability Physics Symposium","volume":"136 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1979-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"17th International Reliability Physics Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IRPS.1979.362889","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2

Abstract

The utilization of plasma etching for selective layer removal of semiconductor device passivation films, polysilicon or substrate silicon, is playing a more and more significant role in delineation of specific failure mechanisms or process introduced anomalies. The advantages of selective removal of materials without destroying the failure site or its morphology are discussed, as well as complementary techniques used in performance of the various analyses. Analysis results are given involving bipolar and FET structures that identify 1. Sites of metal alloy penetration causing excessive leakage currents in bipolar logic circuitry. 2. Opens in test site double level metal interconnection vias due to current stress. 3. Corrosion sites on interconnection metallurgy. 4. FET gate oxide quality after polysilicon gate electrode removal. 5 Test site C-4 terminal interconnection via opens.
失效分析技术和失效机制利用等离子蚀刻
利用等离子体蚀刻技术选择性地去除半导体器件钝化膜,多晶硅或衬底硅,在描述特定失效机制或过程引入的异常方面发挥着越来越重要的作用。讨论了在不破坏失效部位或其形态的情况下选择性去除材料的优点,以及在各种分析性能中使用的补充技术。给出了涉及双极和场效应管结构的分析结果,确定了1。在双极逻辑电路中,金属合金渗透导致泄漏电流过大的部位。2. 由于电流应力,在测试现场打开双水平金属互连通孔。3.互连冶金中的腐蚀部位。4. 多晶硅栅极去除后FET栅极氧化物质量。5 .试验场C-4终端通过开路互连。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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