Process robustness and reproducibility of sub-mm wave flip-chip interconnect assembly

Abstract

The design margins for sub-mm-wave flip-chip transitions in three different topologies, coplanar-to-coplanar, stripline-to-coplanar, and stripline-to-stripline, were verified with the realization and S-parameter measurement of passive chip assemblies, which contain the same wiring architecture as our InP DHBT circuit integration. High yield was observed, and less than 2 dB insertion loss per transition was measured above 300 GHz on the stripline-to-stripline design.