Compensation of ESD and device input capacitance by using embedded inductor on PCB substrate for 3 Gbps SerDes applications

Abstract

We first propose a simple and efficient reactive termination circuit for compensation of the parasitic capacitance which results from the ESD protection circuit and device input capacitance. By using this compensation circuit, the broadband impedance of the receiver circuit is controlled and matched, and the distortion of the high speed signal due to the inherent parasitic capacitance is significantly reduced. A conventional preemphasis circuit is applied concurrently to the design of a high-speed transceiver together with this technique. The required parameter values for the preemphasis circuit and the suggested reactive termination circuit are optimized in the frequency domain. Simulations in the time domain shows an improvement in the eye diagram.