Leakage mechanism and optimized conditioms of Co salicide process for deep-submicron CMOS devices

Abstract

For high performance deep-submicron CMOS devices, the TiN capped Co salicide process is one of the most attractive candidate to reduce the sheet resistances of the narrow gate, source, and drain regions. However, the increased leakage current for a very shallow p-n junction is a serious problem. We clarified a new leakage mechanism of the Co salicided junction. Measurements and simulated results of the leakage current revealed that the leakage current flows from many localized points. These leakage points were caused by CoSi spikes growing from the silicide film, which we observed by TEM analysis. We then optimized the Co salicide process conditions to reduce the leakage current in the ultra-shallow junctions of deep-submicron CMOS devices.