Circuit design for 128Mb PCRAM based on 40nm technology

Abstract

In this paper, a 128Mb phase change random access memory based on phase change Ge2Sb2Te5 alloy has been designed in 40nm 4 metal level CMOS technology. Memory cell is the dual trench epitaxial pn junction diode. According to the feature of the 1D1R memory cell structure, array architecture and chip architecture have been optimized. The read access time is 30ns in simulation. The layout area is 6.6mm × 3.8mm.