{"title":"Membrane design for MCM and BGA substrate test","authors":"J. Cofield","doi":"10.1109/ICMCM.1998.670757","DOIUrl":null,"url":null,"abstract":"Increasing IC complexity is placing new demands on multichip module (MCM) test engineers. Traditional \"bed of nails\" and \"flying probe\" test methods are not adequate to meet the demands of high pin count and density. Design tools need to keep pace with new test methods being employed to address this rising complexity. One approach to solving this problem is the use of a membrane test head. This paper discusses the design software requirements and CAD challenges that result from the membrane approach to substrate test. Some of these new challenges include data translation, test probe assignment and optimization, routing, and inner layer testing. The test methods and design requirements discussed are applicable to multichip, few-chip and ball grid array (BGA) packaging.","PeriodicalId":315799,"journal":{"name":"Proceedings. 1998 International Conference on Multichip Modules and High Density Packaging (Cat. No.98EX154)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1998-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings. 1998 International Conference on Multichip Modules and High Density Packaging (Cat. No.98EX154)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICMCM.1998.670757","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
Increasing IC complexity is placing new demands on multichip module (MCM) test engineers. Traditional "bed of nails" and "flying probe" test methods are not adequate to meet the demands of high pin count and density. Design tools need to keep pace with new test methods being employed to address this rising complexity. One approach to solving this problem is the use of a membrane test head. This paper discusses the design software requirements and CAD challenges that result from the membrane approach to substrate test. Some of these new challenges include data translation, test probe assignment and optimization, routing, and inner layer testing. The test methods and design requirements discussed are applicable to multichip, few-chip and ball grid array (BGA) packaging.