A multi-layered methodology for defect-tolerance of datapath modules in processors

Abstract

Technology scaling increases circuits' susceptibility to manufacturing imperfections and dramatically decreases processor yields. Traditional defect-tolerance approaches add explicit redundant circuitry to improve yield and hence are very expensive for datapath modules in processors. We propose a multi-layered methodology to develop new and efficient defect-tolerance approaches for processors. Specifically, we develop a microarchitecture layer approach for arithmetic logic units (ALU), a circuit layer approach for multipliers, and an ISA layer approach for floating-point units (FPU). We demonstrate that our three approaches improve performance-per-fabricated-die-area of a modern processor core by 3.5%, 2.4%, and at least 9%, and hence collectively provide significant gains.