Runtime Congestion and Crosstalk Aware Router for FPGA Using Jbits3.0 for Partial Reconfigurable Application

Abstract

With the reduction in chip size, the cross talk has become a critical concern among the designers. One of the major techniques to avoid the cross talk effect is to route the critical path in such a way that no interferences occur between the interconnects. In this paper we have proposed a run time congestion and cross talk aware router for FPGA using Jbits3.0. Since, in FPGA routing, resources are fixed so in contrary to ASICs, that, the FPGAs do not have the luxury of utilizing any rerouting options within the wafer-as it requires. So, we routed only those nets having length more than a predetermined critical length or the critical path to avoid cross talk. Hence, congestion and cross talk aware routing can be performed using smaller routing area. Here, we have implemented the router by using class provided by JBits for Xilinx, Vertex-II FPGA (xc2V1000). It has been found that the results are quite encouraging.