A Low Power High Linearity Cryogenic Readout Integrated Circuit with Large Charge Handling Capacity for $10\mu\mathrm{m}$ Pitch $640\times 512$ Infrared Focal Plane Array

Abstract

This paper presents a low power cryogenic readout integrated circuit(ROIC) with large charge handling capacity for $640\times 512$ infrared focal plane array(IRFPA). An innovative structure using two-stage cascaded source followers in output buffer circuit is proposed to reduce the power consumption of the readout integrated circuit and ensure high linearity of the output voltage. Besides, the area of the integration capacitor in pixel array is maintained as large as possible to ensure large charge handling capacity through a special-shape layout structure. The readout integrated circuit implements frame rate of 100Hz, charge handling capacity of 7.28Me−, nonlinearity of 0.87‰ and power consumption of 61mW with $4\times 10\text{MHz}$ output rate when the integration mode is integration while reading(IWR).