Nanoprobing on the SRAM static noise margin (SNM) soft fail analysis

Abstract

As the semiconductor technology continues to scale, the stability and performance of embedded SRAM are growing concerns during the design and analysis stages. Maintaining an acceptable Static Noise Margin (SNM) in the embedded SRAM while scaling the minimum feature size and supply voltage of the integrated circuit (IC) becomes increasingly challenging. As a result, the manufacturing process window continues to shrink. This increases the difficulty for the failure analysis as many soft failures are induced by the reducing process margin. In this paper, a case study on an advanced technology node embedded SRAM soft fail was analyzed. Nanoprobing was employed at the room temperature to do SNM analysis at Metal 1 on the suspected location. Abnormal SNM window was observed at the room temperature analysis. Further analysis at high temperature on the same bit confirmed the soft failure bit. This correlates to the testing failure mode result. This case study is a good example for others who encounter same kind of the embedded SRAM soft failure.