Simple FinFET gate doping technique for dipole-engineered Vt tuning and CET scaling

Abstract

In this paper, we report a Vt tuning technique by dipole-engineering dopant incorporation in the FinFET metal gate stack. Remote interfacial layer scavenging induced by the metal gate dopants has an added advantage of improving the CET, without impacting short channel behavior. Using Al as the dipole-inducing dopant in a FinFET gate stack, a 170mV of positive Vt shift with 0.8Å CETinv reduction was demonstrated. Dopant profiles can be tailored to simply render a CET reduction alone without any Vt tuning, if needed. These results demonstrate key progress towards realizing multi Vt FinFET device architectures for 20nm node and beyond.