Impact of Schottky Barrier on the Performance of Two-Dimensional Material Transistors

S. Su, Jin Cai, E. Chen, Lain‐Jong Li, H. Philip Wong
{"title":"Impact of Schottky Barrier on the Performance of Two-Dimensional Material Transistors","authors":"S. Su, Jin Cai, E. Chen, Lain‐Jong Li, H. Philip Wong","doi":"10.23919/SISPAD49475.2020.9241670","DOIUrl":null,"url":null,"abstract":"Double-gated monolayer two-dimensional (2D) material transistor is expected to offer ideal (~60 mV/dec) subthreshold swing (SS) for gate lengths well below 10 nm. However, the ideal 2D transistor assumes Ohmic contacts whereas a realistic metal/2D Schottky contact can degrade SS. Transport simulations including scattering is necessary to correctly describe carrier thermalization and predict the SS degradation. Scaled 2D transistors with a Schottky barrier height (SBH) smaller than 100 meV and doping concentration in the extension region larger than 2x1013 cm-2 are required to achieve high performance.","PeriodicalId":206964,"journal":{"name":"2020 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/SISPAD49475.2020.9241670","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0

Abstract

Double-gated monolayer two-dimensional (2D) material transistor is expected to offer ideal (~60 mV/dec) subthreshold swing (SS) for gate lengths well below 10 nm. However, the ideal 2D transistor assumes Ohmic contacts whereas a realistic metal/2D Schottky contact can degrade SS. Transport simulations including scattering is necessary to correctly describe carrier thermalization and predict the SS degradation. Scaled 2D transistors with a Schottky barrier height (SBH) smaller than 100 meV and doping concentration in the extension region larger than 2x1013 cm-2 are required to achieve high performance.
肖特基势垒对二维材料晶体管性能的影响
双门控单层二维(2D)材料晶体管有望在栅极长度远低于10 nm时提供理想的(~60 mV/dec)亚阈值摆幅(SS)。然而,理想的二维晶体管假设欧姆接触,而现实的金属/二维肖特基接触会降低SS。包括散射在内的传输模拟对于正确描述载流子热化和预测SS退化是必要的。要实现高性能,需要肖特基势垒高度(SBH)小于100 meV,扩展区的掺杂浓度大于2 × 1013 cm-2。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 求助全文
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信