Versatile HV lateral JFETs design in a 0.18μm SOI superjunction BCD technology

Abstract

This paper presents versatile HV lateral JFET design method on 0.18μm SOI BCD technology to achieve variable Vth(threshold voltage) and Idsat, without DIBL effect over full operating Vds range and scalable breakdown voltage capability on both N-ch and P-ch JFET. The significant advantage of a HV JFET compared to depletion MOSFET is the lower area consumption in real circuit design which due to higher Idsat values at Vgs=0V.