Reduce simultaneous switching jitter in number, spatial, time, and frequency dimensions

Abstract

This paper analyzes high-speed interface simultaneous switching jitter (SSJ) and mathematically describes methods for reducing SSJ in number, spatial, time, and frequency dimensions. Quantitative relationships between SSJ and its major sources — SSO crosstalk, driver PDN SSN, and pre-driver PDN SSN — are discussed. Firmware and hardware methods for SSJ reduction on die, on package, and on PCB from system co-design point of view are described. The effectiveness of SSJ reduction through data encoding is proved mathematically. New concepts, such as effective density of simultaneous switching bits, two-stage selective fixed-length encoding, three-path PDN co-design, are introduced for SSJ reduction in different dimensions. A new PDN design method based on noise to jitter transfer function and jitter sensitivity profiles is described as well. Concepts and methods are validated through system level simulations and measurements.