Challenges in Reliability Assessment of Advanced CMOS Technologies

Abstract

In this paper it was demonstrated that by applying the classical way of reliability lifetime prediction, the reliability of a product can no longer be guaranteed in some cases and for some failure mechanisms. This is caused by reduced reliability margins under the influence of increasing fields, current and power densities on the one hand, by introduction of new materials and devices on the other hand, and by ever increasing failure rate requirements imposed by the market. As a result, the reliability engineers have started to rethink the classical reliability assessment methodology. By taking into account the changes in failure behavior and statistics under influence of scaling trends, and analyzing the impact of such failures on the device and circuit operation, new reliability margins can be gained. This will, however, require more interaction between technology, reliability and design engineers, in order to define realistic failure specifications and new chip failure criteria for each type of circuit. In this paper some elements of such a new reliability assessment methodology have been demonstrated by using oxide breakdown as the failure mechanism for a case study where the classical reliability margins are already reduced to zero. It is expected, however, that for most of the other failure mechanisms a similar trend will emerge, and similar solutions, requiring the interaction with design engineers, will be necessary.